ASIC Engineer, Design for Test

Meta is building custom silicon to power the next generation of infrastructure and computing platforms. As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at scale across Meta's data center infrastructure. In this role, you will define DFT strategies from RTL through silicon bring-up, ensuring manufacturability, diagnosability, and high fault coverage across large, multi-billion gate designs. You will collaborate closely with design, physical implementation, and validation teams to deliver silicon that meets aggressive quality and time-to-market targets.