ASIC & FPGA Design Engineer Sr - E3
Description
Standard Job Description
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You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team within Lockheed Martin Missiles and Fire Control (MFC). Our team creates, prototypes, and fields precision engagement aerospace and defense systems for the U.S. and allied militaries, delivering cutting edge digital solutions that protect the warfighter. |
Basic Qualifications
• Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree preferred
• Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline
• Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog
• Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology
• Experience with FPGA simulation tools such as Synopsys VCS
• Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity
• Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols
• Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators
• Familiarity with Synopsys EDA tools
• Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance
Desired Skills
• LM/MFC design experience and missile program experience
• Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets
• Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP
• Experience implementing NSA algorithms (e.g., AES, counter mode)
• Experience managing configuration control (GitLab preferred)
• Experience with Vivado and Vitis FPGA toolsets
• Experience with UVM and Simulink/HDL Coder integration
• Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment
• Experience with troubleshooting and debugging at board level, including FPGA validation
• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
• Strong communication, collaboration, and presentation abilities
• Controls and digital loop-closure application knowledge
• Networking proficiency with Ethernet switches, routers, firewalls, and debugging tools (tcpdump, Wireshark)
• Active DoD Secret or Top Secret clearance