ASIC & FPGA Design Engineer Sr Stf - E5

Standard Job Description

Join Our Team as a ASIC/FPGA Design Engineer Sr Staff where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment.

Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in:

• Littleton, CO

You will be working a flexible 9x80 schedule in the office full-time.

The information below reflects the standard job description for this position:

Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.

Basic Qualifications

• Experience in the design of FPGA and/or ASIC devices.
• HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
• Willing and able to obtain and maintain a DoD Secret clearance, thus US Citizenship is required for this position.
• Equivalent experience/combined education.
• Acitve Secret Clearance.

Desired Skills

• Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline.
• Understand the basics of Digital Signal Processing (DSP) implementation, and have the ability to implement a defined module or part of an algorithm.
• Experience with DSP methodologies (Nyquist sampling, FFT/IFFT, digital filtering, FIR filters)
• Familiar with MATLAB, C/C++, and VHDL/Verilog DSP implementation.
• Understanding Fixed vs. Floating-Point processing.
• Experience or coursework in the design of FPGA and/or ASIC devices.
• Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
• Knowledge of Forward Error Correction (FEC), interleaving/de-interleaving, hopping/dehopping, modulation/de-modulation, channelizers and reconstructors.
• Experience with ADC and DAC implementation.
• Experience or knowledge of MS Project, JIRA.
• Experience leading projects of multiple engineers, managing schedules. prioritizing work and actively communicating with internal or external stakeholders.
• Knowledge of space-grade/qualified FPGAs and ASICs.
• Experience with Earned Value Management System (EVMS).
• Experience in 5G and/or LTE is a plus.
• Experience mentoring junior engineers.