Design Verification Engineer, Leo Payload FPGA
Posted Updated
Description
Leo Production team FPGA Verification engineer. Creating & Maintaining verification environments and test suites for FPGA based subsystems.
Export Control Requirement
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Must be able to work out of the office 5 days a week.
Key job responsibilities
Verify FPGA solutions to support Amazon Project Leo's satellite communication system. This is a unique opportunity to contribute to a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA based solutions to enable Project Leo. This will focus on verifying digital designs for networking functions using the latest simulation-based verification processes and tools.
In this role you will:
• Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVM
• Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions
• Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;
• Enhance your leadership skills while contributing to a dynamic DV team
• Create reusable Verification IP to be shared across the organization;
• Support implementing upgrades to our process and methodologies.
• Enhance your DV skills as well as your knowledge of Networking while working with subject matter experts;
• Mentor junior engineers
• Participate in the development and deployment of networking and satellite bus FPGAs
A day in the life
Leo Production team FPGA verification engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define and create UVM based simulation test environments intended to characterize and prove out functionality of FPGA designs qualifying them for release to enable Project Leo. This will focus on creating FPGA verification environments and test suites. This role will be using the latest verification flows, processes and tools.
About the team
Project Leo is a new initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Leo FPGA team is responsible for several FPGA designs that are an integral part of the Leo ecosystem.
Export Control Requirement
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Must be able to work out of the office 5 days a week.
Key job responsibilities
Verify FPGA solutions to support Amazon Project Leo's satellite communication system. This is a unique opportunity to contribute to a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA based solutions to enable Project Leo. This will focus on verifying digital designs for networking functions using the latest simulation-based verification processes and tools.
In this role you will:
• Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVM
• Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions
• Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;
• Enhance your leadership skills while contributing to a dynamic DV team
• Create reusable Verification IP to be shared across the organization;
• Support implementing upgrades to our process and methodologies.
• Enhance your DV skills as well as your knowledge of Networking while working with subject matter experts;
• Mentor junior engineers
• Participate in the development and deployment of networking and satellite bus FPGAs
A day in the life
Leo Production team FPGA verification engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define and create UVM based simulation test environments intended to characterize and prove out functionality of FPGA designs qualifying them for release to enable Project Leo. This will focus on creating FPGA verification environments and test suites. This role will be using the latest verification flows, processes and tools.
About the team
Project Leo is a new initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Leo FPGA team is responsible for several FPGA designs that are an integral part of the Leo ecosystem.