Senior SoC Integration Engineer

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

The position is for a Senior SoC Integration Engineer at Lattice Semiconductor. The engineer will be part of the Silicon Integration Team, responsible for integrating IP blocks into the full chip using both digital and custom design flows, while also contributing to full-chip power modeling and silicon correlation in support of other engineering teams.

Key Responsibilities:

• Integrate IP blocks — including DDR PHY — into the full chip using both digital and custom design flows: developing RTL, synthesis, timing constraints (SDC), and timing closure (STA) across multiple IP sources, and resolving DFT integration issues with IP and product teams. Deliver the resulting models, views, and collateral needed for other engineering teams to sign off.

• Support custom and physical design integration tasks, including custom cell design and reuse across the chip, parasitic extraction, and clock-critical signal routing and shielding review ahead of tapeout.

• Collaborate with IP design, product engineering, and test teams on full-chip power modeling: validating current and power assumptions per supply domain, reviewing circuit- and physical-design power simulation results, and correlating simulated power models to silicon bench and production test data to support test screen definition.

Qualifications:

• BS or MS in Electronics, Computer, or Electrical Engineering, with 10+ years of experience in ASIC, SoC, or FPGA design and product development.

• Proven expertise in both custom and digital design implementation for IP and full-chip integration, including RTL coding (Verilog/System Verilog), synthesis, equivalence checking, SDC/STA, and DFT/ATPG flows.

• Familiarity with custom design concepts: transistor-level analysis and circuit characterization and power simulation using industry-standard EDA tools.

• Working knowledge of circuit-level power simulation, CMOS low-power design concepts, and correlating simulated results to silicon/bench measurement data across multiple process nodes/foundries.

• Strong scripting ability (e.g., Python, Perl, TCL, Shell) and excellent communication skills to work across design, test, and product engineering teams; project leadership and product development cycle experience (planning, tapeout, silicon validation) is a plus.

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Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

220,000.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.