Positron AI
Open positions
Senior FPGA Design Engineer
You will own FPGA designs from microarchitecture through lab-based silicon validation. You will design, implement, test, release, and support networking and digital logic functions for FPGA and ASIC targets. You will…
ASIC Architect, Principal (AI Inference)
About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep…
Infrastructure Security Engineer (Senior/Principal)
About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep…
ASIC Physical Design Engineer - DFT, Senior
About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep…
Senior Mechanical Engineer Manufacturing
You will own the mechanical, thermal-mechanical, and enclosure design of rack-mounted AI inference systems. You will create designs, models, drawings, BOMs, and tolerance analyses; lead thermal and structural…
Senior Recruiter Hardware
You will lead full-cycle recruiting for specialized hardware engineering roles, from defining the role and candidate profile through sourcing, interviewing, offers, and closing. You will partner with engineering…
ASIC Architect, Principal (AI Inference)
About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Our first-generation ASIC, Asimov, is a…
ASIC Physical Design Engineer - Power, Senior
About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep…
Platform Software Architect Senior Staff
You will define versioned hardware/software interfaces across current and future accelerator generations. You will connect firmware, operating systems, runtimes, simulation, and tools into a cohesive platform…
Senior Physical Design Engineer - Synth
You will own synthesis, timing convergence, and implementation readiness for assigned ASIC partitions. You will develop constraints and synthesis flows, optimize QoR, close timing, provide RTL feedback, coordinate with…
Senior ASIC Design Engineer
You will lead the definition, implementation, and RTL signoff of critical ASIC and SoC IP blocks. You will own microarchitecture, PPA, integration, timing closure, and methodology improvements; collaborate across…
Senior Design for Test Engineer
You will own end-to-end DFT implementation for AI accelerators, from micro-architecture definition through tapeout and first-silicon bring-up. You will implement and integrate DFT logic in RTL and third-party IP,…
Principal ASIC Design Engineer
You will define microarchitecture and deliver parameterized SystemVerilog RTL for critical ASIC IP blocks and subsystems. You will lead front-end signoff, optimize PPA, integrate interfaces and memory systems, improve…
Senior Software Engineer
You will design and implement high-performance LLM inference software in modern C++. You will optimize vectorization, memory access, threading, scheduling, and data movement across x86 CPUs and FPGAs. You will profile…
Emulation Test Engineer
You will lead pre-silicon validation on the Cadence Palladium platform. You will architect model builds and partitioning, maintain emulation and co-simulation environments, execute interface and memory validation…
Director of Silicon Validation
You will lead pre-silicon verification, hardware emulation, and post-silicon validation through tape-out and production. You will set verification strategy, build emulation and regression infrastructure, lead silicon…
Director of ASIC Design
You will lead design, development, verification, and execution for high-performance AI inference chips. You will define ASIC architecture, microarchitecture, and roadmaps; optimize power, performance, area, and memory…